Intrinsic dual gate oxide mosfet using a damascene gate process

ABSTRACT

Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devicemanufacturing, and in particular to methods for forming semiconductordevices such as metal oxide semiconductor field effect transistors(MOSFETs) and anti-fuses which include at least a dual thicknessdielectric layer.

BACKGROUND OF THE INVENTION

[0002] In current technologies, the threshold voltage of semiconductordevices does not scale with the power supply voltage and ground rulesbecause of the non-scalability of the sub-threshold slope. Thus, theminimum gate oxide thickness and/or maximum wordline boost voltage ofthe array MOSFET is constrained by reliability considerations.

[0003] When used for the support MOSFET, the relatively thick gate oxide(having a thickness of greater than ≈6 nm for deep sub-μm technology)required by the array MOSFET results in degradation in the performanceof the MOSFET device. Furthermore, if a thinner gate oxide is used toimprove the performance of the support circuitry, charge transferefficiency in the device array is compromised as a result of thereliability limitation of the wordline boost voltage.

[0004] Ideally, in such technology, a dual gate oxide thickness isdesired. In the prior art, it is known to subject the array transistorto a dual gate oxidation process or an alternative gate oxidationprocess as compared to the support circuitry. These additional gateoxidation processing steps are costly, and they are also yield limitingsince one must utilize additional processing steps such as, but notlimited to: masking, exposure, etching, oxidizing and strip masking,which grow a second oxide on the entire structure of the MOSFET device.As such, prior art gate oxidation processes are not reliable nor costefficient.

[0005] In view of the drawbacks mentioned above with prior art processesof fabricating MOSFETs, there is a continued need for providing a newand improved method of fabricating a MOSFET and other devices in which adielectric layer, e.g., gate oxide, having a dual thickness can beformed without adding extra processing steps and costs to the overallmanufacturing process.

SUMMARY OF THE INVENTION

[0006] One object of the present invention is to provide a self-alignedMOSFET having low overlap capacitance, and a low gate induced drainleakage (i.e., low electric field), with thin oxide MOSFET properties.

[0007] Another object of the present invention is to provide a method offorming a structure having lightly doped source/drain diffusion regionsthat are self-aligned with the step in the gate dielectric thickness.The term “step” is used herein to denote the region in the gatedielectric wherein an abrupt change in dielectric thickness occurs.

[0008] A further object of the present invention is to provide ananti-fuse device in which significantly lower dielectric rupturevoltages can be employed than heretofore possible with prior artanti-fuse devices.

[0009] An even further object of the present invention is to provide ananti-fuse device in which the programming region of the device istailored made.

[0010] The above objects and advantages are achieved in one embodimentof the present invention by implanting an inhibiting species intopredetermined regions of a semiconductor structure, whereby saidinhibiting species retards the growth of a gate dielectric so as to formdiscrete dielectric regions having different thicknesses.

[0011] Specifically, in this embodiment of the present invention, themethod comprises the steps of:

[0012] (a) forming a mask having an opening therethrough on a structure,said opening having sidewalls;

[0013] (b) implanting an inhibiting species into said structure throughthe opening so as to form an inhibiting region in said structure; and

[0014] (c) growing a dual thickness dielectric layer on the structure insaid opening, wherein the inhibiting region partially inhibits growth ofthe dielectric layer.

[0015] The above-mentioned basic processing steps can be used inconjunction with or without sacrificial sidewall spacers formed in theopening, and with or without a sacrificial oxide layer formed in theopening. The above-mentioned processing steps may also be used inconjunction with a conventional damascene processing scheme or,alternatively, in conjunction with a non-damascene processing scheme.

[0016] Damascene processing is employed in the present invention infabricating MOSFETs that have minium device geometry. Non-damasceneprocessing, while being capable of forming MOSFETS, is limited to largerdevices than which can be fabricated by damascene processing. Moreover,the non-damascene technique permits the formation of anti-fuse devicesthat contain the dual thickness dielectric layer as the anti-fusematerial.

[0017] Alternatively, the dual thickness dielectric may be obtainedutilizing the following processing steps:

[0018] (a′) forming a mask having an opening therethrough on astructure, said opening having sidewalls;

[0019] (b′) implanting a dielectric growth enhancement species into saidstructure through the opening so as to form an enhancing region in saidstructure; and

[0020] (c′) growing a dual thickness dielectric layer on the structurein said opening, wherein the enhancing region partially aids in growthof the dielectric layer.

[0021] This alternative embodiment of the present invention may be usedwith or without sacrificial sidewall spacers; without or without asacrificial oxide layer; in conjunction with a damascene processingscheme; or in conjunction with a non-damascene processing scheme.

[0022] Notwithstanding which method is employed, the present inventionalso comprises a semiconductor device which includes a dual thicknessdielectric as either the gate oxide of a MOSFET or as an anti-fusematerial. Specifically, the semiconductor device of the presentinvention comprises:

[0023] a semiconductor substrate having a gate region formed thereon,wherein said semiconductor substrate and said gate region are separatedby a dielectric that has a dual thickness associated therewith.

[0024] In one embodiment of the present invention, the structurecontains lightly doped source/drain diffusion regions that areself-aligned with the step segment in the dual thickness dielectic.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIGS. 1-7 are pictorial views illustrating the basic processingsteps employed in a first embodiment of the present invention.

[0026] FIGS. 8-13 are pictorial views illustrating the basic processingsteps employed in a variation to the first embodiment of the presentinvention.

[0027] FIGS. 14-19 are pictorial views illustrating the basic processingsteps used in a second embodiment of the present invention.

[0028]FIG. 20 is a pictorial view illustrating an alternative structurethat can be formed by using the method of the present invention inconjunction with a non-damascene processing scheme.

DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention which provides methods for forming adielectric layer having dual thicknesses will now be described in moredetail by referring to the drawings that accompany the presentapplication. It is noted that in the accompanying drawings, like and/orcorresponding elements are referred to by like reference numerals.

[0030] Damascene Embodiments:

[0031] Reference is first made to FIGS. 1-7 which illustrate a firstembodiment of the present invention wherein method steps (a)-(c)mentioned above are used in conjunction with a damascene processingscheme. Specifically, FIG. 1 shows an initial structure that can beemployed in the present invention. The illustrated structure includessemiconductor substrate 10, isolation regions 12, oxide layer 14, andhard mask 16. The structure shown in FIG. 1 is fabricated usingconventional processing techniques well known in the art and it iscomposed of conventional materials that are also well known in the art.

[0032] For example, semiconductor substrate 10 comprises anysemiconducting material including, but not limited to: Si, Ge, SiGe,GaAs, InAs, InP and all other III/V semiconductor compounds. Layeredsubstrates comprising the same or different semiconductor material,e.g., Si/SiGe, and silicon-on-insulators (SOIs) are also contemplatedherein. The substrate may be of the n or p-type depending on the desireddevice to be fabricated.

[0033] Each isolation region 12 is composed of an insulating materialsuch as SiO₂ and each isolation region may be lined with a conventionalliner material. The opening for each isolation region is formed byconventional lithography and etching such as reactive-ion ecthing (RIE)and the insulating material is formed in the opening by any conventionaldeposition process such as chemical vapor deposition (CVD),plasma-assisted CVD, sputtering, reactive-sputtering and other likedeposition processes. Following deposition of the insulating material, aconventional planarization process such as chemical-mechanical polishing(CMP) or grinding may be employed.

[0034] Although trench isolation regions are depicted, the presentinvention is not limited to structures which include the same. Instead,the trench isolation regions may be replaced by LOCOS (local oxidationof silicon) regions or other like isolation regions which are well knownto those skilled in the art. In some embodiments of the presentinvention, especially those involving anti-fuse devices, no isolationregions need be present in the structure.

[0035] Next, oxide layer 14 is formed on the surface of semiconductorsubstrate 10 utilizing a conventional deposition process such as CVD,plasma-assisted CVD, evaporation or sputtering. Alternatively, oxidelayer 14 may be formed by utilizing a conventional thermal growingprocess. The oxide layer is typically composed of SiO₂ and its thicknessis from about 2 to about 200 nm, with a thickness of from about 10 toabout 20 nm being more preferred.

[0036] Hard mask 16 is formed on oxide layer 14 utilizing a conventionaldeposition process such as CVD, plasma-assisted CVD, sputtering,evaporation and other like deposition processes. The hard mask iscomposed of SiN, SiO_(x)N_(y) or other like materials that are capableof acting as a hard mask as well as a polish stop layer. The thicknessof the hard mask is not critical to the present invention, but typicallythe hard mask has a thickness of from about 50 to about 400 nm.

[0037] Next, a conventional photoresist mask 18 is formed on the hardmask using a conventional deposition process such as spin-on coating,CVD, plasma-assisted CVD, evaporation and other like depositionprocesses. The photoresist mask is patterned utilizing conventionallithography including resist exposure and development.

[0038] Next, opening 20 having substantially vertical sidewalls 21 isformed in the structure shown in FIG. 1 using the patterned photoresist.The opening is formed by any conventional dry etching process such asRIE, ion-beam etching, plasma-etching or any combinations thereof. Inone embodiment and as shown in FIG. 2, this etching step may stop onoxide layer 14. Alternatively, and as shown in FIG. 8, this etching stepmay stop on a surface of semiconductor substrate 10. It should be notedthat although only one opening is depicted in the drawings of thepresent invention, the various methods of the present invention workwell when a plurality of openings are formed in the structure.

[0039] At this point in the present invention, an optional well implantregion (not shown in the drawings) may be formed by utilizingconventional ion implantation and activation annealing. The photoresistmay be removed after etching or after the optional well implant has beenperformed.

[0040] Next, optional sacrificial sidewall spacers 22 which may becomposed of an oxide, an oxynitride, a nitride, or a doped glass such asphosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG)or arsenic silicate glass (ASG) may be formed in opening 20 onsubstantially vertical sidewalls 21. The optional sacrificial sidewallspacers may be formed on both substantially vertical sidewalls (See FIG.3), on only one substantially vertical sidewall or neither verticalsidewall. The latter two alternatives are not shown in the drawings ofthe present invention, but the basic concepts thereof can be understoodfrom the various drawings depicted herein. The use of sacrificialspacers is highly preferred in the present invention since these spacersserve as an implant screen for the subsequent implant process.

[0041] It is noted that sacrificial spacers composed of a doped glassmaterial are used in forming a predoped region in the semiconductorsubstrate, See FIG. 9 in this regard.

[0042] The optional sacrificial sidewall spacers are formed utilizing aconventional deposition process such as CVD, plasma-assisted CVD,evaporation, sputtering, or chemical solution deposition and thereaftera conventional dry etch process, as mentioned above, is used in formingthe desired spacer shape.

[0043] Next, as shown in FIG. 4, an inhibiting species 24 such asnitrogen and other like species that are capable of retarding growth ofa dielectric layer are implanted into the substrate using conventionalion implantation so as to form inhibiting region 26 therein. Typically,nitrogen is used in this step of the present invention and the implantis carried out using an ion dosage of from about 1×10¹⁴ to about 1×10¹⁵atoms/cm² at an energy range of from about 10 to about 30 keV. The aboveconditions which are dependent on layer 14 are exemplary and by no waylimit the scope of the present invention.

[0044] Other ion implantation conditions that are capable of forming aninhibiting region in the substrate are thus also contemplated herein.

[0045] Alternatively, instead of using an inhibiting species at thispoint of the present invention, a species that enhances the formation ofthe dielectric ( i.e., “dielectric growth enhancement species”) may beimplanted so as to form a dielectric growth enhancing region in thesubstrate which aids in the growth of the dielectric layer. When such analternative embodiment is employed, the region containing the dielectricgrowth enhancement agent will provide a thicker dielectric as comparedto regions that do not contain the same. This effect is opposite to theeffect illustrated in the drawings of the present invention wherein athinner dielectric region is formed in areas containing the inhibitingspecies. For clarity, this alternative embodiment is not illustrated inthe drawings, however the final structure obtained would be similar tothe ones depicted in the present invention.

[0046] When the alternative embodiment is employed, a growth enhancementspecies, which could also be labeled as 24, such as oxygen, argon andother like species that are capable of enhancing the growth of adielectric layer are implanted into the substrate using conventional ionimplantation so as to form an enhancing region (which could also bedesignated as 26) therein. Typically, oxygen is used in this alternativestep of the present invention and the implant is carried out using anion dosage of from about 1×10¹⁴ to about 1×10¹⁶ atoms/cm² at an energyrange of from about 10 to about 35 keV. As before, these conditions arealso exemplary and by no way limit the scope of the present invention.

[0047] For the sake of brevity, the description that follows will makereference only to the inhibiting species and region with theunderstanding however that the alternative embodiment mentioned above isalso applicable. Again, the effect of the alternative embodiment isopposite to the one depicted in the drawings, i.e., the presence of theenhancing region causes the formation of a dielectric that is thickerthan in regions which do not contain the same.

[0048] It should be noted that by using the above mentioned sacrificialsidewall spacers one can tailor where the inhibiting region is formed inthe substrate. For example, when two sacrificial spacers are present inthe opening, the inhibiting region is formed substantially in the centerof the opening. Thus, when the subsequent dielectric layer is grown insuch a structure, the center region will contain a dielectric that isthinner than the abutting end regions which include the sacrificialspacers. Likewise, when only one sacrificial spacer is present, theinhibiting region is formed in an area abutting the sacrificial spacerand that area will contain a thinner dielectric than the remainingregions which include the spacer. When no sacrificial spacers arepresent, tailoring of the dual thickness dielectric may be achievedutilizing a masked ion implantation process. Alternatively, when nosacrificial sidewall spacers are employed, tailoring may be had by usingboth the inhibiting species and the enhancement species, and byimplanting each species into different regions in the opening.

[0049] Following the formation of the inhibiting region in thesubstrate, the optional sacrificial spacers and the oxide layer in theopening are stripped utilizing an etching process that is highlyselective in removing these regions so as to expose the underlyingsubstrate. Specifically, the etching process used in the step of thepresent invention may include any dry etching process, wet chemicaletching process or a combination thereof. The optional sacrificialspacers and oxide layer in the opening may be removed at the same timeusing a single etching process, or these regions may be removed atdifferent times utilizing a combination of the same or different etchingprocesses. Alternatively, a chemical-down stream etching (CDE) processmay be used in forming the sacrificial spacers and the oxide layer.

[0050] Next, as shown in FIG. 5, dielectric layer 28 is grown in theopening on the exposed portions of the substrate utilizing aconventional growing process such as a gate oxidation process. As shownin FIG. 5, dielectric layer 28 will also be formed in part of thesubstrate. Because of the presence of the inhibiting region previouslyformed in the substrate, the dielectric that is grown in areasoverlaying the inhibiting region is thinner than in areas that do notcontain the inhibiting region; the opposite effect is observed when anenhancement species is employed.

[0051] The dielectric that is grown is typically composed of an oxidesuch as SiO₂ and reference numeral 29 is used in defining the stepsegment(s) which signifies the region in dielectric layer 28 wherein anabrupt change in thickness is first observed.

[0052] Typically, the dielectric layer is grown by heating the structurein the presence of an oxidizing ambient such as O₂, ozone, or NO at atemperature of from about 800° to about 1100° C. for a time period ofabout from 100 seconds to about 20 minutes. Other temperatures and timesmay also be employed in the present invention so long as they arecapable of growing dielectric layer 28.

[0053] Next, as shown in FIG. 6, the opening is filled with a conductivematerial 30 utilizing any conventional deposition process including, butnot limited to: CVD, plasma-assisted CVD, sputtering, evaporation,plating (electro- and electroless), reactive-sputtering, chemicalsolution deposition and other like deposition processes.

[0054] The conductive material used in this step of the presentinvention includes: polysilicon, conductive metals such as W, Pt, Au,Ag, Co and Ti, metallic silicides such as WSi_(x), TiSi_(x) or CoSi_(x),metallic nitrides, or any combination thereof: for example, a multilayercomprising polysilicon and a conductive metal or metallic silicide maybe used. It should be noted that when MOSFETs are formed, the substratemay be, but not necessarily, a different conductivity type than theconductive material. In the case of anti-fuse devices, the substrate andthe conductive material may be, but not necessarily, formed of the sameconductivity type material, i.e., n-type or p-type materials.

[0055] An optional capping layer (not shown in the drawings of thepresent invention) composed of SiN or TiN may be formed by conventionaldeposition processes on the exposed top layer of conductive material 30.

[0056] Following deposition of the conductive material into the opening,a conventional planarization process such as CMP may be employed toprovide the planar structure illustrated in FIG. 6.

[0057]FIG. 7 illustrates the MOSFET structure that is formed afterconducting a conventional damascene etch back process in which hard mask16 abutting the dielectric layer and conductive material (hereinafterreferred to as the gate region) is removed. The damascene etch backprocess employed in the present invention utilizes a chemical etchantthat is highly selective for removing hard mask material as compared tothe surrounding materials.

[0058] Spacers 32 are formed on the exterior sidewalls on the gateregion utilizing the same process as used in forming the sacrificialsidewall spacers. Thus, CVD and RIE can be employed in forming spacers32. It is also possible to form spacers 32 by a directional depositionprocess. The spacers used in the step of the present invention may becomprised of a nitride, an oxynitride or an oxide. In anti-fuse devices,spacers 32 may be omitted.

[0059] Next, any oxide layer 14 surrounding the gate region not coveredby spacers 32 is removed utilizing an etching process that is highlyselective in removing oxide as compared to the surrounding materialspresent in the structure.

[0060] Following formation of the spacers and removal of the oxide layersurrounding the gate region, diffusion regions 34 having differentconductivities are formed in the substrate utilizing conventional ionimplantation and activation annealing. As shown, the diffusion regionsare self-aligned with the step segments in the dielectric layer.

[0061] The above description and FIGS. 1-7 illustrate one possibleembodiment of the present invention, the following description whichmakes reference to FIGS. 8-13 shows a variation to the embodimentillustrated above.

[0062]FIG. 8 illustrates a structure that is used in this alternativeembodiment of the present invention. Specifically, the structure shownin FIG. 8 includes substrate 10, isolation regions 12, oxide layer 14,hard mask 16, patterned photoresist 18, and opening 20 that extends tothe surface of substrate 10.

[0063] The structure shown in FIG. 8 is fabricated utilizing the sameprocessing steps as described hereinabove in providing the structureshown in FIGS. 1-2, except that etching removes both the hard mask andthe oxide layer.

[0064] The patterned photoresist is removed and thereafter sacrificialspacers 22 composed of doped silicate glass (See FIG. 9) are formed inopening 20 using a conventional deposition and etching process. Asacrificial oxide layer 36 (See FIG. 9) is then formed in the opening onthe surface of the substrate not containing the doped silicate glassspacers using the same or different processes as was used in formingoxide layer 14. When a sacrificial oxide layer is formed in the opening,it may have the same or different thickness as oxide layer 14.

[0065] Following the formation of the sacrificial oxide layer, thedopant within the doped spacers are driven into the substrate using anyconventional annealing process that is capable of driving-in andactivating the dopant so as to form predoped regions 38 (See FIG. 9) inthe structure. As illustrated in FIG. 9, the predoped regions arecontained substantially within the regions of the substrate that arebeneath the doped spacers.

[0066] FIGS. 10-13 show the structure through various processing stepsthat are equivalent to those described above in regard to FIGS. 4-7;therefore no further description of the various processing steps arenecessary. It is noted that in this embodiment, it is also possible touse only one doped silicate glass spacer. When the embodiment shown inFIGS. 8-13 is employed the diffusion regions are self-aligned to thestep segment in the dielectric layer.

[0067] Non-damascene Embodiments:

[0068] In addition to the damascene embodiments mentioned above, themethod of the present invention can also be implemented withnon-damascene embodiments. In the non-damascene embodiments, the initialstructure employed is shown in FIG. 14. Specifically, the structureshown in FIG. 14 includes semiconductor substrate 10, isolation regions12, and oxide layer 14. No hard mask is employed in the non-damasceneembodiments.

[0069] Next, as shown in FIGS. 14-15, photoresist mask 18 is formed onthe oxide layer and the mask is patterned by conventional lithography.Opening 20 which extends to a top surface of oxide layer 14 is formed inthe patterned photoresist by RIE or another like dry etching processes.

[0070] Following the formation of opening 20 and optionally thesacrificial spacers (not shown here for clarity) in the structure,inhibiting species 24 is implanted as described above so as to provideinhibiting region 26 in the structure. This step of the presentinvention is shown in FIG. 16. As in the previous embodiment, theinhibiting species may be replaced with a dielectric growth enhancementspecies which forms an enhancing region in the substrate that aids inthe growth of the dielectric.

[0071] Next, as shown in FIG. 17, the oxide layer (and, if present, theoptional sacrificial spacers) in the opening is removed by one of theabove mentioned etching processes and dielectric layer 28 is formed inthe opening as described above. As before, the dielectric has dualthicknesses wherein the thinnest regions are over areas that include theinhibiting regions, or alternatively, when an enhancement species isemployed the thinnest region of the dielectric will be in regions thatdo not contain the enhancement species.

[0072] Conductive material 30 is formed in the opening on the dualthickness dielectric layer (see FIG. 18) and the photoresist mask isthereafter stripped. Sidewall spacers 32 are formed on the exteriorsidewalls of the gate region and any exposed oxide layer about the gateregion is removed utilizing a selective etch process. Diffusion regions34 are then formed in the substrate providing the structure shown inFIG. 19.

[0073]FIG. 20 shows a final structure in which the center portion of theopening has a thicker gate dielectric as compared to the abutting endportions. This structure is formed utilizing the same basic processingsteps as illustrated in FIGS. 14-18 except that a portion of thepatterned mask remains in the center of the opening during implantingthe inhibiting species. This structure shown in FIG. 20 is especiallypractical for anti-fuse devices where the highest field would be locatedbetween the gate and the edge regions which are thinner than the centerregion. This is important in antifuse devices since the thinner regionscan be programmed to control the blowing of the device.

[0074] While this invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

Having thus described our invention in detail, what we claim as new anddesire to secure by the Letters Patent is:
 1. A method for fabricating adual thickness dielectric layer in a semiconductor device comprising:(a) forming a mask having an opening therethrough on a structure, saidopening having sidewalls; (b) implanting an inhibiting species into saidstructure through the opening so as to form an inhibiting region in saidstructure; and (c) growing a dual thickness dielectric layer on thestructure in said opening, wherein the inhibiting region partiallyinhibits growth of the dielectric layer.
 2. The method of claim 1wherein said structure includes at least a semiconductor substratehaving an oxide layer formed thereon.
 3. The method of claim 2 furthercomprising a hard mask formed on said oxide layer.
 4. The method ofclaim 1 wherein step (a) includes lithography and etching.
 5. The methodof claim 1 further comprising forming at least one sacrificial sidewallspacer in said opening on said sidewalls.
 6. The method of claim 5wherein said at least one sacrificial sidewall spacer is formed bydeposition and etching.
 7. The method of claim 5 wherein two sacrificialsidewall spacers are formed in the opening.
 8. The method of claim 5wherein said at least one sidewall spacer is composed of an oxide, anoxynitride, or a doped silicate glass.
 9. The method of claim 8 whereinsaid at least one sacrificial sidewall spacer is composed of a dopedsilicate glass and dopant from said doped silicate glass in driven-intothe structure by annealing so as to form at least one predoped region.10. The method of claim 1 further comprising forming a sacrificial oxidelayer in said opening prior to conducting step (b).
 11. The method ofclaim 1 wherein said inhibiting species is nitrogen.
 12. The method ofclaim 11 wherein said nitrogen is implanted at an ion dosage of fromabout 1×10¹⁴ to about 1×10¹⁵ atoms/cm² at an energy of from about 10 toabout 30 keV.
 13. The method of claim 1 wherein said inhibiting regionis formed substantially in the center of said opening.
 14. The method ofclaim 1 wherein said inhibiting region is formed in proximity to atleast one sidewall of said opening.
 15. The method of claim 1 whereinsaid inhibiting region is formed in proximity to both sidewalls of saidopening and the center of the opening does not contain said inhibitingregion.
 16. The method of claim 1 wherein said dielectric is an oxide.17. The method of claim 1 wherein said dielectric is grown by anoxidation process.
 18. The method of claim 1 wherein a conductivematerial is formed on said dielectric layer.
 19. The method of claim 1further comprising (d) a damascene processing scheme.
 20. The method ofclaim 19 wherein said damascene processing scheme includes etch backingutilizing a chemical etchant, spacer formation, oxide removal anddiffusion formation.
 21. The method of claim 1 further comprising (d) anon-damascene processing scheme.
 22. The method of claim 21 wherein saidnon-damascene processing scheme includes stripping said mask, spacerformation, oxide removal and diffusion formation.
 23. A method forfabricating a dual thickness dielectric layer in a semiconductor devicecomprising: (a′) forming a mask having an opening therethrough on astructure, said opening having sidewalls; (b′) implanting a dielectricgrowth enhancement species into said structure through the opening so asto form an enhancement region in said structure; and (c′) growing a dualthickness dielectric layer on the structure in said opening, wherein theenhancing region partially aids in growth of the dielectric layer. 24.The method of claim 23 wherein said dielectric growth enhancementspecies is oxygen or argon.
 25. A semiconductor device comprising: asemiconductor substrate having a gate region formed thereon, whereinsaid semiconductor substrate and said gate region are separated by adielectric that has a dual thickness associated therewith.
 26. Thesemiconductor device of claim 25 wherein said gate region is a componentof an antifuse device or a metal oxide semiconductor field effecttransistor.
 27. The semiconductor device of claim 25 further comprisingdoped regions formed in said semiconductor substrate, wherein said dopedregions are self-aligned with a step portion of said dielectric.
 28. Thesemiconductor device of claim 25 wherein said dielectric having thethinnest region can be programmed.